Binary to RNS encoder with Modulo 2n+1 Channel in Diminished-1 Number System

Architecture of binary to residue number system encoder based on the moduli set {2 1,2 ,2 1} n n n   , and architecture of encoder with modulo 2 1 n  channel in the diminished-1 representation instead of the standard modulo 2 1 n  channel are presented. We consider the binary numbers with dynamic range of proposed moduli set which is 3 2 2 n n  . Within this dynamic range, 3n -bit binary number is partitioned into three n -bit parts and converted to standard residue numbers, or converted to two standard residues and a residue in the diminished-1 representation. Our approach enables a unified design for the moduli set adders. The proposed architecture can be utilized in conjunction with any fast binary adder without requiring any extra hardware. The encoder architecture with diminished-1 encoded channel has been mapped on an Xilinx FPGA chip.